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M40Z300 M40Z300W
NVRAM CONTROLLER for up to EIGHT LPSRAM
s s s s
s
s s s
s
s
CONVERT LOW POWER SRAMs into NVRAMs PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when VCC is OUT-OF-TOLERANCE TWO INPUT DECODER ALLOWS CONTROL for up to 8 SRAMs (with 2 devices active in parallel) CHOICE of SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: - M40Z300: VCC = 4.5V to 5.5V THS = VSS 4.5V VPFD 4.75V THS = VOUT 4.2V V PFD 4.5V - M40Z300W: VCC = 3.0V to 3.6V THS = VSS 2.8V VPFD 3.0V VCC = 2.7V to 3.3V THS = VOUT 2.5 VPFD 2.7V RESET OUTPUT (RST) for POWER ON RESET LESS THAN 12ns CHIP ENABLE ACCESS PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT(R) TOP, or a 16-LEAD SOIC (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY BATTERY LOW PIN (BL)
SNAPHAT (SH) Battery
16
28 1
1
SO16 (MQ)
SOH28 (MH)
Figure 1. Logic Diagram
VCC B+(1)
THS E B A M40Z300 M40Z300W
VOUT BL E1CON E2CON E3CON E4CON RST
DESCRIPTION The M40Z300/W NVRAM Controller is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition.
VSS B-(1)
NOTE: 1. For 16-pin SOIC package only.
AI02242
March 2000
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M40Z300, M40Z300W
Figure 2A. SOIC28 Connections Figure 2B. SOIC16 Connections
VOUT NC NC RST NC A NC B NC BL NC NC THS VSS
1 28 27 2 26 3 25 4 24 5 23 6 7 M40Z300 22 8 M40Z300W 21 20 9 19 10 18 11 17 12 16 13 15 14
AI02243
VCC E NC NC NC E1CON E2CON NC E3CON NC NC NC E4CON NC
VOUT NC RST A B BL THS VSS
( ) = M40Z300W
1 16 15 2 14 3 4 M40Z300 13 5 M40Z300W 12 11 6 7 10 8 9
VCC B+ (B-) E E1CON E2CON E3CON E4CON B- (B+)
AI03624
Table 1. Signal Names
THS E E1CON-E4CON A, B RST BL VOUT VCC VSS B+ B- NC Threshold Select Input Chip Enable Input Conditioned Chip Enable Output Decoder Inputs Reset Output (Open Drain) Battery Low Output (Open Drain) Supply Voltage Output Supply Voltage Ground Positive Battery Pin Negative Battery Pin Not Connected Internally
When an invalid V CC condition occurs, the conditioned chip enable outputs (E1 CON to E4CON ) are forced inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28 pin, 330 mil SOIC provides sockets with gold plated contacts for direct connection to a separate SNAPHAT housing containing the battery. The SNAPHAT housing has gold plated pins which mate with the sockets, ensuring reliable connection. The housing is keyed to prevent improper insertion. This unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process which greatly reduces the board manufacturing process complexity of either directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a "SNAP". The 16 pin SOIC provides battery pins for an external user supplied battery.
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M40Z300, M40Z300W
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation M40Z300 M40Z300W SNAPHAT SOIC Value 0 to 70 -40 to 85 -55 to 125 -0.3 to VCC +0.3 -0.3 to 7 -0.3 to 4.6 20 1 Unit C C V V mA W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
OPERATION The M40Z300/W, as shown in Figure 4, can control up to four (eight, if placed in parallel) standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E1CON to E4CON ) output pins follow the chip enable (E) input pin with timing shown in Table 7. An internal switch connects V CC to V OUT. This switch has a voltage drop of less than 0.3V (IOUT1). When V CC degrades during a power failure, E1CON to E4CON are forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40Z300 the power fail detection value associated with VPFD is selected by the Threshold Select (THS) pin and is shown in Table 6A. For the M40Z300W, the THS pin selects both the supply voltage and VPFD as shown in Table 6B. Note: In either case, THS pin must be connected to either VSS or VOUT.
If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWPT, E1CON to E4CON are unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time exceeds t F (See Table 7). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to V OUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage V OHB to the SRAM and can supply current IOUT2 (see Table 6A/6B). When V CC rises above VSO, VOUT is switched back to the supply voltage. Outputs E1CON to E4CON are held inactive for tCER (120ms maximum) after the power supply has reached V PFD, independent of the E input, to allow for processor stabilization (see Figure 6).
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M40Z300, M40Z300W
Table 3. Truth Table
Inputs E H L L L L B X L L H H A X L H L H E1CON H L H H H E2CON H H L H H Outputs E3CON H H H L H E4CON H H H H L
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Figure 3. AC Testing Load Circuit
DATA RETENTION LIFETIME CALCULATION Most low power SRAMs on the market today can be used with the M40Z300/W NVRAM Controller. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z300/W and SRAMs to be Don't Care once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second Chip Enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I CCDR value of
DEVICE UNDER TEST
333
CL = 50pF
1.73V
CL includes JIG capacitance
AI02393
the M40Z300/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can then be divided by this current to determine the amount of data retention available (see Table 8). CAUTION: Take care to avoid inadvertent discharge through V OUT and E1CON-E4CON after battery has been attached. For a further more detailed review of lifetime calculations, please see Application Note AN1012.
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M40Z300, M40Z300W
Figure 4. Hardware Hookup
3.0V, 3.3V or 5V
VCC
VOUT VCC VCC CMOS SRAM 0.1F E E 0.1F E VCC CMOS SRAM 0.1F E VCC CMOS SRAM
0.1F M40Z300 M40Z300W 0.1F E1CON E2CON E3CON E4CON RST BL
CMOS SRAM
A B E Threshold THS VSS
To Microprocessor To Battery Monitor Circuit
AI02395
POWER-ON RESET OUTPUT All microprocessors have a reset input which forces them to a known state when starting. The M40Z300/W has a reset output (RST) pin which is guaranteed to be low within tWPT of V PFD (See Table 7). This signal is an open drain configuration. An appropriate pull-up resistor should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when V CC equals VSS.
Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize. TWO TO FOUR DECODE The M40Z300/W includes a 2 input (A, B) decoder which allows the control of up to 4 independent SRAMs. The Truth Table for these inputs is shown in Table 3.
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M40Z300, M40Z300W
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 8 10 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. Outputs deselected.
Table 6A. DC Characteristics for M40Z300 (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ICC VIL VIH VOL VOH VOHB IOUT1 IOUT2 ICCDR THS VPFD VSO Parameter Input Leakage Current Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (open drain) (2) Output High Voltage VOH Battery Back-up (3) VOUT Current (Active) VOUT Current (Battery Back-up) Data Retention Mode Current (4) Threshold Select Voltage Power-fail Deselect Voltage (THS = VSS) Power-fail Deselect Voltage (THS = VOUT) Battery Back-up Switchover Voltage VSS 4.5 4.2 4.6 4.35 3.0 IOL = 4.0mA IOL = 10mA IOH = -2.0mA IOUT2 = -1.0A VOUT > VCC -0.3 VOUT > VCC -0.2 VOUT > VBAT -0.3 100 100 VOUT 4.75 4.5 2.4 2.0 2.9 3.6 250 150 Test Condition 0V VIN VCC Outputs open -0.3 2.2 3 Min Typ Max 1 6 0.8 VCC + 0.3 0.4 0.4 Unit A mA V V V V V V mA mA A nA V V V V
Note: 1. Outputs deselected. 2. For RST & BL pins (Open Drain). 3. Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 4. Measured with V OUT and E1CON - E4CON open.
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M40Z300, M40Z300W
Table 6B. DC Characteristics for M40Z300W (TA = 0 to 70C; VCC = 3V to 3.6V or 2.7V to 3.3V)
Symbol ILI (1) ICC VIL VIH VOL VOH VOHB IOUT1 IOUT2 ICCDR THS VPFD VSO Parameter Input Leakage Current Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (open drain) (2) Output High Voltage VOH Battery Back-up (3) VOUT Current (Active) VOUT Current (Battery Back-up) Data Retention Mode Current (4) Threshold Select Voltage Power-fail Deselect Voltage (THS = VSS) Power-fail Deselect Voltage (THS = VOUT) Battery Back-up Switchover Voltage VSS 2.8 2.5 2.9 2.6 2.5 IOL = 4.0mA IOL = 10mA IOH = -2.0mA IOUT2 = -1.0A VOUT > VCC -0.3 VOUT > VCC -0.2 VOUT > VBAT -0.3 100 100 VOUT 3.0 2.7 2.4 2.0 2.9 3.6 150 100 Test Condition 0V VIN VCC Outputs open -0.3 2.0 2 Min Typ Max 1 4 0.8 VCC + 0.3 0.4 0.4 Unit A mA V V V V V V mA mA A nA V V V V
Note: 1. Outputs deselected. 2. For RST & BL pins (Open Drain). 3. Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 4. Measured with V OUT and E1CON - E4CON open.
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M40Z300, M40Z300W
Table 7. Power Down/Up AC Characteristics (TA = 0 to 70C)
Symbol tF (1) tFB (2) tR tEDL Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time M40Z300 Chip Enable Propagation Delay Low M40Z300W M40Z300 Chip Enable Propagation Delay High M40Z300W A, B set up to E Chip Enable Recovery VPFD (max) to RST High M40Z300 tWPT tRB Write Protect Time M40Z300W VSS to VPFD (min) VCC Rise Time 40 1 250 s s 0 40 40 40 120 120 150 20 ns ns ms ms s 20 10 ns ns Min 300 150 10 12 Max Unit s s s ns
tEDH tAS tCER tREC
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min).. 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
BATTERY LOW PIN The M40Z300/W automatically performs battery voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V CC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. SNAPHAT top should be replaced with valid VCC applied to the device. The M40Z300/W only monitors the battery when a nominal V CC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.
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M40Z300, M40Z300W
Figure 5. Power Down Timing
VCC VPFD (max) VPFD VPFD (min) VSO
tF tFB
E tWPT VOHB E1CON-E4CON
RST
AI02398B
Figure 6. Power Up Timing
VCC VPFD (max) VPFD VPFD (min) VSO
tR tRB E tEDH E1CON-E4CON VOHB tREC RST
AI02399B
tCER
tEDL
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M40Z300, M40Z300W
Figure 7. Address-Decode Time
A, B tAS
E tEDL E1CON-E4CON tEDH or tEDL
AI02551
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E and EXCON
Table 8. Battery Table
Part Number M4Z28-BR00SH M4Z32-BR00SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
VCC NOISE AND NEGATIVE GOING TRANSIENTS ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 8. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI00622
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M40Z300, M40Z300W
Table 9. Ordering Information Scheme
Example: Supply Voltage and Write Protect Voltage 300 = VCC = 4.5V to 5.5V THS = VSS 4.5V VPFD 4.75V THS = VOUT 4.2V VPFD 4.5V 300W = VCC = 3.0V to 3.6V THS = VSS 2.8V VPFD 3.0V VCC = 2.7V to 3.3V THS = VOUT 2.5V VPFD 2.7V Package MH(1,2) = SOH28 MQ = SO16 Temperature Range 1 = 0 to 70 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel M40Z300W MH 1 TR
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form. 2. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are functionally equivalent (see package drawing section for details). Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 10. Revision History
Date March 1999 03/08/00 First Issue Document Layout changed SO16 package added Battery Capacity changed (Table 8) Revision Details
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M40Z300, M40Z300W
Table 11. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 9. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
12/16
M40Z300, M40Z300W
Table 12. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
Figure 10. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
13/16
M40Z300, M40Z300W
Table 13. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
Figure 11. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
14/16
M40Z300, M40Z300W
Table 14. SO16 - 16 lead Plastic Small Outline, 300 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 0.38 0.41 0 16 0.10 1027 8 1.27 0.10 0.38 0.23 10.11 7.44 - 10.16 Min. Max. 2.59 0.30 0.51 0.25 10.49 7.54 - 10.41 0.015 0.016 0 16 0.004 0.050 8 0.050 0.004 0.015 0.009 0.398 0.293 - 0.400 Typ. Min. Max. 0.102 0.012 0.020 0.010 0.413 0.297 - 0.410 inches
Figure 12. SO16 - 16 lead Plastic Small Outline, 300 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale.
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M40Z300, M40Z300W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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